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data sheet november 2001 L9219A/g low-cost line interface with reverse battery and dual current limit features n basic forward/reverse battery slic functionality at a low cost n pin compatible with agere systems inc. l9217 and l9218 slics n low active power (typical 138 mw during on-hook transmission) n low-power scan mode for low-power, on-hook power dissipation (52 mw typical) n distortion-free, on-hook transmission n convenient operating states: forward active-low current limit forward active-high current limit reverse active-low current limit reverse active-high current limit low-power scan disconnect (high impedance) n minimal external components required n two gain options to optimize the codec interface n adjustable supervision functions: off-hook detector with hysteresis ring trip detector n logic controlled high and low current limit n ramped rate of battery reversal n thermal protection with thermal shutdown indica- tion description this general-purpose electronic subscriber loop interface circuit (slic) is optimized for low cost, while still providing a satisfactory set of features. this part is a pin-for-pin replacement for the agere l9217 and l9218 slics. the l9219 requires a 5 v power supply and single battery to operate. this device offers forward and reverse battery operation. the rate of battery rever- sal may be ramped to meet international require- ments. additionally, a low-power scan mode, wherein all circuitry except the off-hook supervision is shut down to conserve power, is available. the dc current limit may be programmed via a single external resistor. via the logic table, the current limit may be increased a nominal 42% above the value set by the i prog resistor, giving the user a high-low current limit option. device overhead is fixed and is adequate for 3.14 dbm into 900 w of on-hook transmission. both the loop supervision and ring trip supervision functions are offered with user-controlled thresholds via external resistors. the l9219 is offered with a receive gain that is opti- mized for interface to a first-generation type codec (L9219A). it is also offered with a gain option that is optimized for interface to a third- or fourth-generation type codec (l9219g). in both cases, minimizing external components required at this interface. data control is via a parallel data control scheme. the device is available in a 28-pin plcc package. it is built by using a 90 v complementary bipolar (cbic) process.
2 agere systems inc. data sheet november 2001 with reverse battery and dual current limit L9219A/g low-cost line interface features ......................................................................1 description...................................................................1 pin information ............................................................4 functional description .................................................6 absolute maximum ratings (at ta = 25 c) ................7 recommended operating conditions .........................7 electrical characteristics .............................................8 ring trip requirements ..........................................12 test configurations ...................................................13 applications ...............................................................15 dc applications........................................................19 battery feed.........................................................19 current limit.........................................................19 overhead voltage ............................................... 19 rate of battery reversal ......................................20 loop range..........................................................20 off-hook detection...............................................20 ring trip detection ............................................. 21 longitudinal balance...............................................21 ac design ................................................................22 codec types ........................................................22 ac interface network ............................................22 receive interface .................................................22 example 1: real termination (first- generation codec) ...............................................23 example 2: complex termination (first- generation codec) ...............................................25 power derating .......................................................27 pin-for-pin compatibility with l9217/l9218 ............27 pcb layout information ............................................27 outline diagram.........................................................28 28-pin plcc ...........................................................28 ordering information..................................................29 figures page figure 1. functional diagram...................................3 figure 2. 28-pin plcc.............................................4 figure 3. ring trip circuits ....................................12 figure 4. l9219 basic test circuit.........................13 figure 5. metallic psrr.........................................13 figure 6. longitudinal psrr .................................13 figure 7. longitudinal balance ..............................14 figure 8. rfi rejection ..........................................14 figure 9. longitudinal impedance..........................14 figure 10. ac gains..................................................14 figure 11. basic loop start application circuit using t7504-type codec............15 figure 12. basic loop start application circuit using t8536-type codec............17 figure 13. loop current vs. loop voltage .............. 19 figure 14. off-hook detection circuit ..................... 20 figure 15. ring trip equivalent circuit and equivalent application .................... 21 figure 16. ac equivalent circuit .............................. 23 figure 17. interface circuit using first- generation codec ( 5 v battery) .......... 26 figure 18. interface circuit using first- generation codec (5 v only codec) ..... 26 tables page table 1. pin descriptions ..................................... 4 table 2. input state coding .................................. 6 table 3. supervision coding ................................ 6 table 4. power supply .......................................... 8 table 5. 2-wire port .............................................. 9 table 6. analog pin characteristics .................... 10 table 7. ac feed characteristics ........................ 11 table 8. logic inputs and outputs ...................... 12 table 9. parts list for loop start application circuit using t7504-type codec ......... 16 table 10. 200 w + 680 w || 0.1 mf first- generation codec design parameters . 17 table 11. parts list for loop start application circuit using t8536-type codec ......... 18 table 12. fb1/fb2 values vs. typical ramp time ...................................................... 20 table of contents contents page figures page
agere systems inc. 3 data sheet november 2001 with reverse battery and dual current limit L9219A/g low-cost line interface description (continued) figure 1. functional diagram C + C + + C a = 1 a = C1 power conditioning and reference bgnd agnd i prog v cc cf1 pt pr rtsn rtsp lcth ring trip detector loop closure detector battery feed state control b0 rcvp rcvn b1 nstat fb1 + + C C tip/ring current sense b2 a version gain = 3.93 g version gain = 1 forward and reverse battery dcout vtx tg txi vitr C + ax rectifier 3 aac b = 9.66 cf2 fb2 b = 41 v/a tsd thermal shutdown 12-3557 (f).c
4 agere systems inc. data sheet november 2001 with reverse battery and dual current limit L9219A/g low-cost line interface pin information figure 2. 28-pin plcc table 1. pin descriptions plcc symbol type description 1 i prog i current-limit program input. a resistor to dcout sets the dc current limit of the device. the value of current limit set via this resistor may be increased via logic control (see state table for additional detail). 2 fb2 polarity reversal slowdown. connect a capacitor to ground to control the rate of bat- tery reversal. 3 fb1 polarity reversal slowdown. connect a capacitor to ground to control the rate of bat- tery reversal. 4 v cc 5 v power supply. 5 rcvp i receive ac signal input (noninverting). this high-impedance input controls the ac differential voltage on tip and ring. 6 rcvn i receive ac signal input (inverting). this high-impedance input controls the ac differ- ential voltage on tip and ring. vtx txi vitr nstat nc rtsp rcvn dcout v bat pr 5 6 7 8 9 10 11 4212827 3 12 14 15 16 17 18 13 25 24 23 22 21 20 19 i prog b0 cf1 pt bgnd b1 b2 agnd 28-pin plcc lcth rcvp cf2 rtsn tsd nc fb2 fb1 v cc 26 tg 28-pin plcc 12-3558 (f)
agere systems inc. 5 data sheet november 2001 with reverse battery and dual current limit L9219A/g low-cost line interface pin information (continued) table 1. pin descriptions (continued) plcc symbol type description 7 lcth i loop closure threshold input. connect a resistor to dcout to set off-hook threshold. 8 dcout o dc output voltage. this output is a voltage that is directly proportional to the abso- lute value of the differential tip/ring current. 9 v bat battery supply. negative high-voltage power supply. 10 pr i/o protected ring. the output of the ring driver amplifier and input to loop sensing cir- cuitry. connect to the loop through overvoltage protection. 11 cf2 filter capacitor 2. connect a 0.1 m f capacitor from this pin to agnd. 12 cf1 filter capacitor 1. connect a 0.47 m f capacitor from this pin to pin cf2. 13 b2 i state control input. b0, b1, and b2 determine the state of the slic. see table 2. pin b2 has internal pull-down. 14 b1 i state control input. b0, b1, and b2 determine the state of the slic. see table 2. pin b1 has internal pull-down. 15 b0 i state control input. b0, b1, and b2 determine the state of the slic. see table 2. pin b0 has internal pull-down. 16 agnd analog signal ground. 17 bgnd battery ground. ground return for the battery supply. 18 pt i/o protected tip. the output of the tip driver amplifier and input to loop sensing cir- cuitry. connect to loop through overvoltage protection. 19 rtsn i ring trip sense negative. connect this pin to the ringing generator signal through a high-value resistor. 20 rtsp i ring trip sense positive. connect this pin to the ring relay and the ringer series resistor through a high-value resistor. 21 nc no connect. 22 nstat o ring trip detector output/loop detector output. when low, this logic output indi- cates that ringing is tripped or that an off-hook condition exists. 23 vitr o ac output voltage. the voltage at this point is directly proportional to the differential tip/ring current. 24 txi i ac/dc separation. connect a 0.1 m f capacitor from this point to vtx. 25 vtx o ac and dc output voltage. this output is a voltage that is directly proportional to the differential tip/ring current. 26 tg transmit gain. connect an 8.06 k w from tg to vtx to set the transmit gain of the slic. 27 tsd o thermal shutdown. when high, this logic output indicates the device is in thermal shutdown. 28 nc no connect.
6 agere systems inc. data sheet november 2001 with reverse battery and dual current limit L9219A/g low-cost line interface functional description table 2. input state coding table 3. supervision coding b0 b1 b2 state/definition 1 1 1 powerup, forward battery. normal talk and battery feed state. pin pt is positive with respect to pr. on-hook transmission is enabled. current limit is set per r prog resistor. 1 0 1 powerup, reverse battery. normal talk and battery feed state. pin pt is negative with respect to pr. on-hook transmission is enabled. current limit is set per r prog resistor. 1 1 0 powerup, forward battery, high current limit. normal talk and battery feed state. pin pt is positive with respect to pr. on-hook transmission is enabled. current limit is a nominal 1.4 times higher than setting per r prog resistor. 1 0 0 powerup, reverse battery, high current limit. normal talk and battery feed state. pin pt is negative with respect to pr. on-hook transmission is enabled. current limit is a nominal 1.4 times higher than setting per r prog resistor. 0 1 1 low-power scan. except for off-hook detection, all circuits are shut down to conserve power. pin pt is positive with respect to pin pr. on-hook transmission is disabled. 0 0 1 disconnect. the tip and ring amplifiers are turned off, and the slic goes to a high-impedance state (>100 k w ). supervision outputs read on hook. device will power up in this state. 0 0 0 disconnect. the tip and ring amplifiers are turned off, and the slic goes to a high-impedance state (>100 k w ). supervision outputs read on hook. device will power up in this state. 0 1 0 low-power scan. except for off-hook suppression, all circuits are shut down to conserve power. pin pt is positive with respect to pin pr. on-hook transmission is disabled. nstat tsd 0 = off-hook or ring trip. 1 = on-hook and no ring trip. 0 = normal device operation. 1 = device is in thermal shutdown.
agere systems inc. 7 data sheet november 2001 with reverse battery and dual current limit L9219A/g low-cost line interface absolute maximum ratings (at t a = 25 c) stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. note: the ic can be damaged unless all ground connections are applied before, and removed after, all other connections. furtherm ore, when powering the device, the user must guarantee that no external potential creates a voltage on any pin of the device that exceeds the device ratings. some of the known examples of conditions that cause such potentials during powerup are the following: 1. an inductor connected to tip and ring can force an overvoltage on v bat through the protection devices if the v bat connection chatters. 2. inductance in the v bat lead could resonate with the v bat filter capacitor to cause a destructive overvoltage. recommended operating conditions parameter symbol min typ max unit 5 v power supply v cc 7.0 v battery (talking) supply v bat C75 v logic input voltage C0.5 7.0 v analog input voltage C7.0 7.0 v maximum junction temperature t j 150 c storage temperature range t stg C40 125 c relative humidity range r h 5 95 % ground potential difference (bgnd to agnd) 3 v pt or pr fault voltage (dc) v pt , v pr v bat C 5 3 v pt or pr fault voltage (10 x 1000 m s) v pt , v pr v bat C 15 15 v current into ring trip inputs i rtsp , i rtsn 240 m a parameter min typ max unit ambient temperature C40 85 c v cc supply voltage 4.75 5.0 5.25 v v bat supply voltage C24 C48 C70 v
8 agere systems inc. data sheet november 2001 with reverse battery and dual current limit L9219A/g low-cost line interface electrical characteristics minimum and maximum values are testing requirements in the temperature range of 25 c to 85 c and battery range of C24 v to C70 v. these minimum and maximum values are guaranteed to C40 c based on component simulations and design verification of samples, but devices are not tested to C40 c in production. the test circuit shown in figure 4 is used, unless otherwise noted. positive currents flow into the device. typical values are characteristics of the device design at 25 c based on engineering evaluations and are not part of the test requirements. supply values used for typical characterization are v cc = 5.0 v, v bat = C48 v, unless otherwise noted. table 4. power supply 1. this parameter is not tested in production. it is guaranteed by design and device characterization. 2. careful thermal design as a function of maximum battery, loop length, maximum ambient temperature package thermal resistance, airflow, pcb board layers, and other related parameters must ensure that thermal shutdown temperature is not exceeded under normal use c ondi- tions. 3. airflow, pcb board layers, and other factors can greatly affect this parameter. parameter min typ max unit power supplypowerup, no loop current: i cc i bat (v bat = C48 v) power dissipation (v bat = C48 v) 4.6 C2.4 138 5.6 C2.7 158 ma ma mw power supplyscan, no loop current: i cc i bat (v bat = C48 v) power dissipation (v bat = C48 v) 2.8 C0.8 52 3.8 C1.0 67 ma ma mw power supplydisconnect, no loop current: i cc i bat (v bat = C48 v) power dissipation (v bat = C48 v) 1.6 C0.12 14 ma ma mw power supply rejection 500 hz to 3 khz (see figure 5 and figure 6) 1 : v cc v bat 30 40 db db thermal protection shutdown (t jc ) 3 150 165 c thermal resistance, junction to ambient ( q ja ) 2, 3 : natural convection 2s2p board natural convection 2s0p board wind tunnel 100 linear feet per minute (lfpm) 2s2p board wind tunnel 100 linear feet per minute (lfpm) 2s0p board 30 43 27 36 c/w c/w c/w c/w
agere systems inc. 9 data sheet november 2001 with reverse battery and dual current limit L9219A/g low-cost line interface electrical characteristics (continued) table 5. 2-wire port 1. the longitudinal current is independent of dc loop current. 2. current-limit i lim is programmed by a resistor, r prog , from pin i prog to dcout. i lim is specified at the loop resistance where current limiting begins (see figure 13). 3. this parameter is not tested in production. it is guaranteed by design and device characterization. 4. specification is reduced to |v bat1 + 10.5 v| minimum when v bat1 = C70 v at 85 c. 5. longitudinal balance of circuit card will depend on loop series protection resistor matching and magnitude. more information is available in the applications section of this document. parameter min typ max unit tip or ring drive current = dc + longitudinal + signal currents 80 ma signal current 15 marms longitudinal current capability per wire 1 8.5 15 marms dc loop current limit 2 : allowed range including tolerance 3 accuracy (r loop = 100 w , v bat = C48 v) 15 5 45 ma % powerup open loop voltage levels: common-mode voltage differential voltage v bat = C48 v 4 (gain = 2) differential voltage v bat = C48 v 4 (gain = 7.86) |v bat + 7.5| |v bat + 8.0| v bat /2 |v bat + 6.5| |v bat + 6.5| |v bat + 5.9| |v bat + 5.9| v v v disconnect state: leakage 10 150 m a dc feed resistance (for i loop below regulation level) (does not include protection resistor) 70 100 w loop resistance range (C3.17 dbm overload into 900 w ; not including protection): i loop = 20 ma at v bat = C48 v 1800 w longitudinal to metallic balance ieee ? std. 455 (see figure 7) 5 : 200 hz to 3400 hz 58 61 db metallic to longitudinal balance (open loop): 200 hz to 4 khz 40 db rfi rejection (see figure 8) 3 , 0.5 vrms, 50 w source, 30% am mod 1 khz: 500 khz to 100 mhz C55 C45 dbv
10 agere systems inc. data sheet november 2001 with reverse battery and dual current limit L9219A/g low-cost line interface electrical characteristics (continued) table 6. analog pin characteristics 1. loop closure threshold is programmed by resistor r lcth from pin lcth to pin dcout. 2. this parameter is not tested in production. it is guaranteed by design and device characterization. 3. i n is the sourcing current at rtsn. guaranteed if i n is within 5 m a to 30 m a. parameter min typ max unit differential pt/pr current sense (dcout): gain (pt/pr to dcout) offset voltage at i loop = 0 121 C100 125 129 100 v/a mv loop closure detector threshold (rlcth = 22.1 k w ) 1 : on-hook to off-hook threshold (scan mode) off-hook to on-hook threshold (active mode) 8.8 6.0 13.6 10.2 ma ma ring trip comparator: input offset voltage 2 internal voltage source current at input rtsp 3 C9.1 i n C 0.5 10 C8.6 i n C8.1 i n + 0.6 mv v m a rcvn, rcvp: input bias current input resistance C0.2 1 C1 m a m w
agere systems inc. 11 data sheet november 2001 with reverse battery and dual current limit L9219A/g low-cost line interface electrical characteristics (continued) table 7. ac feed characteristics 1. with a first-generation codec, this parameter is set by external components. any complex impedance r 1 + r2 || c between 150 w and 1300 w can be synthesized. with a third-generation codec, this parameter is set by a codec or by a combination of a codec and an exte rnal network. 2. this parameter is not tested in production. it is guaranteed by design and device characterization. 3. use this gain option with a first-generation or third-generation codec. 4. use this gain option with an agere third-generation codec. parameter min typ max unit ac termination impedance 1 150 1300 w longitudinal impedance at pt/pr 2 0 w total harmonic distortion200 hz to 4 khz 2 : off-hook on-hook 0.3 1.0 % % transmit gain, f = 1 khz (pt/pr to vitr) (current limit) C391 C403 C415 v/a L9219A, open loop: receive + gain, f = 1 khz (rcvp to pt/pr) 3 receive C gain, f = 1 khz (rcvn to pt/pr) 3 l9219g, open loop: receive + gain, f = 1 khz (rcvp to pt/pr) 4 receive C gain, f = 1 khz (rcvn to pt/pr) 4 7.62 C7.62 1.94 C1.94 7.86 C7.86 2.00 C2.00 8.09 C8.09 2.06 C2.06 gain vs. frequency (transmit and receive) (600 w termination; reference 1 khz 2 ): 200 hz to 300 hz 300 hz to 3.4 khz 3.4 khz to 16 khz 16 khz to 266 khz C1.00 C0.3 C3.0 0.0 0.0 C0.1 0.05 0.05 0.3 2.5 db db db db gain vs. level (transmit and receive)(reference 0 dbv 2 ): C55 db to +3 db C0.05 0 0.05 db 2-wire idle-channel noise (600 w termination): psophometric 2 c-message 3 khz flat 2 C87 2 10 C77 12 20 dbmp dbrnc dbrn transmit idle-channel noise: psophometric 2 c-message 3 khz flat 2 C82 7 15 C77 12 20 dbmp dbrnc dbrn
12 12 agere systems inc. data sheet november 2001 with reverse battery and dual current limit L9219A/g low-cost line interface electrical characteristics (continued) table 8. logic inputs and outputs all outputs are open collectors with internal, 30 k w pull-down resistor. input pins have internal pull-down or some method to power up in the disconnect state. ring trip requirements n ringing signal: voltage, minimum 35 vrms, maximum 100 vrms. frequency, 17 hz to 33 hz. crest factor, 1.2 to 1.6. n ring trip: 100 ms (typical). n pretrip: the circuits in figure 3 will not cause ring trip. figure 3. ring trip circuits parameter symbol min typ max unit input voltages: low level (permissible range) high level (permissible range) v il v ih C0.5 2.0 0.4 2.4 0.7 v cc v v input currents: low level (v cc = 5.25 v, v i = 0.4 v) high level (v cc = 5.25 v, v i = 2.4 v) i il i ih 0 +10 +4 +24 +10 +50 m a m a output voltages (open collector with internal pull-up resistor): low level (v cc = 4.75 v, i ol = 200 m a) high level (v cc = 4.75 v, i oh = C20 m a) v ol v oh 0 2.4 0.2 0.4 v cc v v ring ring 100 w 10 k w tip tip 2 m f 8 m f 12-2572 (f).f
agere systems inc. 13 data sheet november 2001 with reverse battery and dual current limit L9219A/g low-cost line interface test configurations 12-3559c (f) figure 4. l9219 basic test circuit figure 5. metallic psrr figure 6. longitudinal psrr v bat v cc 0.1 m f0.1 m f 0.47 m f 0.1 m f r loop 43.2 k w 22.1 k w b1 nstat v bat bgnd v cc agnd i prog lcth rtsp rtsn vitr rcvp b0 cf1 cf2 L9219A slic tg 8.06 k w 100 w /600 w 2 m w 274 k w 2 m w 402 w v bat 50 w 50 w ring tip xmt 75 k w rcv rcvn 46 k w 19.4 k w dcout b2 vtx txi 0.1 m f pr pt tsd v s 4.7 m f 100 w v bat or v cc disconnect v t/r v bat or v cc tip ring basic test circuit + C psrr = 20log v s v t/r 900 w bypass capacitor 12-2582 (f).b v s 4.7 m f 100 w v bat or v cc disconnect bypass capacitor 56.3 w v bat or v cc tip ring basic test circuit psrr = 20log v s v m 67.5 w 10 m f 10 m f 67.5 w v m + C 12-2583 (f).b
14 agere systems inc. data sheet november 2001 with reverse battery and dual current limit L9219A/g low-cost line interface test configurations (continued) figure 7. longitudinal balance v s = 0.5 vrms 30% am 1 khz modulation, f = 500 khz1 mhz device in powerup mode, 600 w termination. figure 8. rfi rejection figure 9. longitudinal impedance figure 10. ac gains tip ring basic test circuit longitudinal balance = 20 log v s v m 368 w 100 m f 100 m f 368 w v m + C v s 12-2584 (f).c basic test circuit tip ring v bat 0.01 m f 0.01 m f 600 w 2.15 m f 82.5 w 82.5 w hp ? 4935a tims 50 w 1 2 4 6, 7 l7591 v s 5-6756 (f).b tip ring basic test circuit + C + C i long i long v pt v pr z long = or d v pt d i long d v pr d i long 12-2585 (f).a tip ring basic test circuit 600 w v t/r + C g xmt = v xmt v t/r g rcv = v t/r v rcv xmt rcv v s 12-2587 (f).e
agere systems inc. 15 data sheet november 2001 with reverse battery and dual current limit L9219A/g low-cost line interface applications a basic loop start reference circuit, using bused ringing with the l9219 slic and the t7504 first-generation codec, is shown in figure 11. this circuit is designed for a 200 w + 680 w || 0.1 m f complex termination impedance and transhybrid. transmit gain is set at 0 dbm and receive gain is set at C7 dbm. figure 11. basic loop start application circuit using t7504-type codec table 9 shows the design parameters of the application circuit shown in figure 11. components that are adjusted to program these values are also shown. table 9. 200 w + 680 w || 0.1 m f first-generation codec design parameters design parameter parameter value components adjusted loop closure threshold 10 ma r lcth dc loop current limit 25 ma r prog 2-wire signal overload level 3.14 dbm ac termination impedance 200 w + 680 w || 0.1 m f r t1 , r gp , r rcv, r gp1, r gs, c gs hybrid balance line impedance 200 w + 680 w || 0.1 m f r hb1 transmit gain 0 dbm r t2 , r x, r n1, r n2, c n receive gain C7 dbm r rcv , r gp , r t1 r prog 35.7 k w r lcth 22.1 k w r pt 50 w l7591 r pr pt 18 1 7 lcth 8 dcout 50 w pr 10 rtsp 20 r ts1 402 w rtsn 19 r tsn 3.32 m w v ring v bat cf2 11 cf1 12 c f1 0.47 m f agnd 16 bgnd 17 i prog v bat 9 c bat 0.1 m f rcvp rcvn 5 6 r gp 30.1 k w r t1 71.5 k w r t2 80.6 k w r rcv 137 k w r hb1 357 k w r x 158 k w gsx vf r o dx dr fsx fsr mclk 1/4 t7504 codec pcm highway control and clock C + l9219 slic c rts1 0.015 m f r tsp 2.94 m w c f2 0.1 m f v bat +2.4 v c b2 0.47 m f 22 supervision outputs b1 b0 14 15 control inputs c gn 0.1 nf r n2 18.2 k w r n1 143 k w nstat b2 13 vitr 23 txi 24 vtx 25 tg 26 c b 0.1 m f r gp1 8.06 k w r gs 2.37 k w c gs 6.8 nf tip ring emr c b1 0.47 m f v cc 4 v cc c cc 0.1 m f 27 tsd lcas 12-3560 (f).g
16 agere systems inc. data sheet november 2001 with reverse battery and dual current limit L9219A/g low-cost line interface applications (continued) table 10. parts list for loop start application circuit using t7504-type codec name value function integrated circuits slic l9219 subscriber loop interface circuit (slic). protector agere l7591 secondary protection. ringing relay agere l7581/2/3 or emr switches ringing signals. codec t7504 first-generation codec. overvoltage protection r pt 50 w , fusible protection resistor. r pr 50 w , fusible protection resistor. power supply c bat1 0.1 m f, 20%, 100 v v bat filter capacitor. c cc 0.1 m f, 20%, 10 v v cc filter capacitor. c f1 0.47 m f, 20%, 100 v with c f2 , improves idle-channel noise. c f2 0.1 m f, 20%, 100 v with c f1 , improves idle-channel noise. dc characteristics r prog 35.7 k w , 1%, 1/16 w set low current limit. ac characteristics c b1 0.47 m f, 20%, 10 v ac/dc separation capacitor. c b2 0.47 m f, 20%, 10 v ac/dc separation capacitor. c b 0.1 m f, 20%, 10 v dc blocking capacitor. r t1 71.5 k w , 1%, 1/16 w with r gp and r rcv , sets ac termination impedance. r rcv 137 k w , 1%, 1/16 w with r gp and r t1 , sets receive gain. r gp 30.1 k w , 1%, 1/16 w with r t1 and r rcv , sets ac termination impedance and receive gain. r t2 80.6 k w , 1%, 1/16 w with r x , sets transmit gain in codec. r x 158 k w , 1%, 1/16 w with r t2 , sets transmit gain in codec. r hb1 357 k w , 1%, 1/16 w sets hybrid balance. c gs 6.8 nf, 10%, 10 v with r gs , provides gain shaping for termination impedance matching. r gs 2.37 k w , 1%, 1/16 w with c gs , provides gain shaping for termination impedance matching. r gp1 8.06 k w , 1%, 1/16 w sets dc transmit gain of slic. c n 0.1 nf, 20%, 10 v with r n1 and r n2 high frequency compensation. r n1 143 k w , 1%, 1/16 w with c n and r n2 high frequency compensation. r n2 18.2 k w , 1%, 1/16 w with r n1 and c n high frequency compensation. supervision r lcth 22.1 k w , 1%, 1/16 w sets loop closure (off-hook) threshold. r ts1 402 w , 5%, 2 w ringing source series resistor. c rts1 0.015 m f, 20%, 10 v with r tsn , r tsp , forms filter pole. r tsn 3.32 m w , 1%, 1/16 w with r tsp , sets threshold. r tsp 2.94 m w , 1%, 1/16 w with c rts1 , r tsn , sets threshold.
agere systems inc. 17 data sheet november 2001 with reverse battery and dual current limit L9219A/g low-cost line interface applications (continued) a basic loop start reference circuit, using bused ringing with the l9219 slic and the t8536 third-generation codec, is shown in figure 12. figure 12. basic loop start application circuit using t8536-type codec r prog 35.7 k w r lcth 22.1 k w r pt 50 w l7591 r pr pt 18 1 7 lcth 8 dcout 50 w pr 10 rtsp 20 r ts1 510 w rtsn 19 r tsn 3.4 m w v ring v bat cf2 11 cf1 12 c f1 0.47 m f agnd 16 bgnd 17 l9219 slic c rts1 0.015 m f r tsp 2.94 m w c f2 0.1 m f rcvn nstat 6 dr2 fs bclk 1/4 t8536 pcm highway control and clock b0 b1 15 14 rcvp 5 vf r on vf x i vf r op slic0a slic3a slic2a dgnd dx1 dx2 dr1 c vdd 0.1 m f v dd codec b2 13 slic4a 22 vitr 23 tip ring emr v bat 9 c bat 0.1 m f v bat txi 24 vtx 25 tg 26 c b 0.1 m f r gp1 8.06 k w c b1 0.1 m f txi i prog v cc 4 c cc 0.1 m f v cc lcas r cin 20 m w 12-3561 (f).d
18 agere systems inc. data sheet november 2001 with reverse battery and dual current limit L9219A/g low-cost line interface applications (continued) table 11. parts list for loop start application circuit using t8536-type codec name value function integrated circuits slic l9219 subscriber loop interface circuit (slic). protector agere l7591 secondary protection. ringing relay agere l7581/2/3 or emr switches ringing signals. codec t8536 third-generation codec. overvoltage protection r pt 50 w , fusible protection resistor. r pr 50 w , fusible protection resistor. power supply c bat1 0.1 m f, 20%, 100 v v bat filter capacitor. c cc 0.1 m f, 20%, 10 v v cc filter capacitor. c f1 0.47 m f, 20%, 100 v with c f2 , improves idle-channel noise. c f2 0.1 m f, 20%, 100 v with c f1 , improves idle-channel noise. dc characteristics r prog 35.7 k w , 1%, 1/16 w set low current limit. ac characteristics c b1 0.1 m f, 20%, 10 v ac/dc separation capacitor. c b 0.1 m f, 20%, 10 v dc blocking capacitor. r gp1 8.06 k w , 1%, 1/16 w sets dc transmit gain of slic. r cin 20 m w , 5%, 1/16 w dc bias. supervision r lcth 22.1 k w , 1%, 1/16 w sets loop closure (off-hook) threshold. r ts1 510 w , 5%, 2 w ringing source series resistor. c rts1 0.015 m f, 20%, 10 v with r tsn and r tsp , forms second 2 hz filter pole. r tsn 3.4 m w , 1%, 1/16 w with r tsp , sets threshold. r tsp 2.94 m w , 1%, 1/16 w with r tsn , sets threshold.
agere systems inc. 19 data sheet november 2001 with reverse battery and dual current limit L9219A/g low-cost line interface applications (continued) dc applications battery feed the dc feed characteristic can be described by: where: i l = dc loop current. v t/r = dc loop voltage. | v bat | = battery voltage magnitude. v oh = overhead voltage. this is the difference between the battery voltage and the open loop tip/ring voltage. r l = loop resistance, not including protection resistors. r p = protection resistor value. r dc = slic internal dc feed resistance. notes: v bat = C48 v. i lim = 22 ma. r dc1 = 80 w . figure 13. loop current vs. loop voltage starting from the on-hook condition and going through to a short circuit, the curve passes through the follow- ing two regions: region 1: on-hook and low loop currents. the slope corresponds to the dc resistance of the slic, r dc1 (default is 70 w typical). the open circuit voltage is the battery voltage minus the overhead voltage of the device, v oh (default is 6.5 v typical). these values are suitable for most applications, but can be adjusted if needed. for more information, see the sections entitled adjusting dc feed resistance and adjusting overhead voltage. region 2: current limit. the dc current is limited to a starting value determined by external resis- tor r prog , the logic table, an internal current source, and the gain from tip/ring to pin vitr. current limit with the logic inputs set to 11 (a low current limit active state), current limit with a 100 w load is given by the fol- lowing: 0.637 r prog (k w ) + 2 ma = i lim x (ma) via the logic table, the current limit can be increased a nominal 42% from the value set by the r prog resistor. the relationship between low current limit and high current limit is as follows: = 0.7 overhead voltage in order to drive an on-hook ac signal, the slic must set up the tip and ring voltage to a value less than the battery voltage. the amount that the open loop voltage is decreased relative to the battery is referred to as the overhead voltage and is expressed as the following equation: v oh = |v bat | C (v pt C v pr ) without this buffer voltage, amplifier saturation will occur and the signal will be clipped. the l9219 is auto- matically set at the factory to allow undistorted on-hook transmission of a 3.14 dbm signal into a 900 w loop impedance. v t/r v bat v oh C () r l r l 2r p r dc ++ --------------------------------------------- = i l v bat v oh C r l 2r p r dc ++ --------------------------------- - = 01020 50 0 20 30 40 50 loop voltage (v) 30 40 10 loop current (ma) 1 12.5 k w C1 r dc1 i lim tested i lim onset 12-3050 (f).i i limit low () i limit high () ---------------------------------- -
20 20 agere systems inc. data sheet november 2001 with reverse battery and dual current limit L9219A/g low-cost line interface applications (continued) dc applications (continued) rate of battery reversal the rate of battery reversal is controlled or ramped by capacitors fb1 and fb2. a chart showing fb1/fb2 val- ues versus typical ramp rate is given below. leave fb1/fb2 open if it is not desired to ramp the rate of battery reversal. table 12. fb1/fb2 values vs. typical ramp time loop range the equation below can be rearranged to provide the loop range for a required loop current: off-hook detection the loop closure comparator has built-in longitudinal rejection, eliminating the need for an external 60 hz filter. the loop closure detection threshold is set by resistor r lcth . the supervision output bit (nstat) is high in an on-hook condition. the off-hook comparator goes low during an off-hook condition: i tr (ma) = 0.4167 r lcth (k w ) C 1.9 ma active off-hook to on-hook i tr (ma) = 0.4167 r lcth (k w ) + 2.7 ma scan on-hook to off-hook figure 14. off-hook detection circuit c fb1 /c fb2 transition time 0.01 m f 20 ms 0.1 m f 220 ms 0.22 m f 440 ms 0.47 m f 900 ms 1.0 m f 1.8 s 1.22 m f2.25 s 1.3 m f 2.5 s 1.4 m f 2.7 s 1.6 m f 3.2 s r l v bat v oh C i l ---------------------------- 2r p C r dc C = r l itr r p r p ring C + C + dcout r lcth lcth nstat tip 0.125 v/ma 0.05 ma 12-2553 (f).f
agere systems inc. 21 data sheet november 2001 with reverse battery and dual current limit L9219A/g low-cost line interface applications (continued) dc applications (continued) ring trip detection the ring trip circuit is a comparator that has a special input section optimized for this application. the equivalent circuit is shown in figure 15, along with its use in an application using unbalanced, battery-backed ringing. figure 15. ring trip equivalent circuit and equivalent application ring trip detection threshold is given by the following equation: i th (ma) = longitudinal balance the slic is graded to certain longitudinal balance specifications. the numbers are guaranteed by testing (figure 5 and figure 8). however, for specific applications, the longitudinal balance may also be determined by termination impedance, protection resistance, and especially by the mismatch between protection resistors at tip and ring. this can be illustrated by the following equation: lb = 20 x log where: lb: longitudinal balance rp: protection resistor value in w zt: magnitude of the termination impedance in w e : protection resistor mismatch in w d : slic internal tip/ring sensing mismatch the d can be calculated using the above equation with these exceptions: e = 0, zt = 600 w, rp = 100 w, and the longitudinal balance specification on a specific code. now with d available, the equation will predict the actual longitudinal balance for rp, zt, and e . be aware that zt may vary with frequency for complex impedance applications. + C r tsp r loop 15 k w 8.6 v i p = i n r tsn 3.32 m w/ 3.40 m w c rts1 0.015 m f phone hook switch rc phone v ring v bat nstat r tsp i n r tsn C + 2.94 m w r s 402 w/ 510 w 2799 (f) rtsn m w () 0.015 rtsp m w () C + [] v bat 8.6 C [] 1000 rtsn m w () 0.015 + [] r s ------------------------------------------------------------------------------------------------------------------------------- ------------------------------------------ 368 rp + () 368 zt rp C + () 3682zt2 C rp [] d e + () -------------------------------------------------------------------------------------------
22 22 agere systems inc. data sheet november 2001 with reverse battery and dual current limit L9219A/g low-cost line interface applications (continued) ac design codec types at this point in the design, the codec needs to be selected. the interface network between the slic and codec can then be designed. there are four key ac design parameters. termination impedance is the impedance looking into the 2-wire port of the line card. it is set to match the impedance of the telephone loop in order to minimize echo return to the telephone set. transmit gain is measured from the 2-wire port to the pcm highway, while receive gain is done from the pcm highway to the transmit port. finally, the hybrid balance network cancels the unwanted amount of the receive signal that appears at the transmit port. below is a brief codec feature summary. first-generation codecs. these perform the basic filtering, a/d (transmit), d/a (receive), and m -law/a-law companding. they all have an op amp in front of the a/d converter for transmit gain setting and hybrid bal- ance (cancellation at the summing node). depending on the type, some have differential analog input stages, differential analog output stages, 5 v only or 5 v oper- ation, and m -law/a-law selectability. these are avail- able in single and quad designs. this type of codec requires continuous time analog filtering via external resistor/capacitor networks to set the ac design param- eters. an example of this type of codec is the agere t7504 quad 5 v only codec. this type of codec tends to be the most economical in terms of piece part price, but tends to require more external components than a third-generation codec. furthermore, ac parameters are fixed by the external r/c network, so software control of ac parameters is difficult. third-generation codecs. this class of devices includes all ac parameters set digitally under micropro- cessor control. depending on the device, it may or may not have data control latches. additional functionality sometimes offered includes tone plant generation and reception, ttx generation, test algorithms, and echo cancellation. again, this type of codec may be 5 v only or 5 v operation, single quad or 16-channel, and m -law/a-law or 16-bit linear coding selectable. exam- ples of this type of codec are the agere t8535/6 (5 v only, quad, standard features), t8533/4 (5 v only, quad with echo cancellation), and the t8531/36 (5 v only 16-channel with self-test). ac interface network the ac interface network between the l9219 and the codec will vary depending on the codec selected. with a first-generation codec, the interface between the l9219 and codec actually sets the ac parameters. with a third-generation codec, all ac parameters are set dig- itally, internal to the codec; thus, the interface between the l9219 and this type of codec is designed to avoid overload at the codec input in the transmit direction, and to optimize signal-to-noise ratio (s/n) in the receive direction. receive interface because the design requirements are very different with a first- or third-generation codec, the l9219 is offered with two different receive gains. each receive gain was chosen to optimize, in terms of external com- ponents required, the ac interface between the l9219 and codec. with a first-generation codec, the termination imped- ance is set by providing gain shaping through a feed- back network from the slic vitr output to the slic rcvn/rcvp inputs. the l9219 provides a transcon- ductance from t/r to vitr in the transmit direction and a single ended to differential gain in the receive direc- tion from either rcvn or rcvp to t/r. assuming a short from vitr to rcvn or rcvp, the maximum impedance that is seen looking into the slic is the product of the slic transconductance times the slic receive gain, plus the protection resistors. the various specified termination impedance can range over the voice band as low as 300 w up to over 1000 w . thus, if the slic gains are too low, it will be impossible to syn- thesize the higher termination impedances. further- more, the termination that is achieved will be far less than what is calculated by assuming a short for slic output to slic input. in the receive direction, in order to control echo, the gain is typically a loss, which requires a loss network at the slic rcvn/rcvp inputs, which will reduce the amount of gain that is available for ter- mination impedance. for this reason a high-gain slic is required with a first-generation codec.
agere systems inc. 23 data sheet november 2001 with reverse battery and dual current limit L9219A/g low-cost line interface applications (continued) ac design (continued) receive interface (continued) with a third-generation codec, the line card designer has different concerns. to design the ac interface, the designer must first decide upon all termination imped- ance, hybrid balances, and transmission level points (tlp) requirements that the line card must meet. in the transmit direction, the only concern is that the slic does not provide a signal that is too hot and overloads the codec input. thus, for the highest tlp that is being designed to, given the slic gain, the designer, as a function of voice band frequency, must ensure that the codec is not overloaded. with a given tlp and a given slic gain, if the signal will cause a codec overload, the designer must insert some sort of loss, typically a resis- tor divider, between the slic output and codec input. in the receive direction, the issue is to optimize s/n. again, the designer must consider all the considered tlps. the idea is, for all desired tlps, to run the codec at or as close as possible to its maximum output signal, to optimize the s/n. remember noise floor is constant, so the hotter the signal from the codec, the better the s/n. the problem is, if the codec is feeding a high-gain slic, either an external resistor divider is needed to knock the gain down to meet the tlp requirements, or the codec is not operating near maxi- mum signal levels, thus compromising the s/n. it appears the solution is to have a slic with a low gain, especially in the receive direction. this will allow the codec to operate near its maximum output signal (to optimize s/n), without an external resistor divider (to minimize cost). note also that some third-generation codecs require the designer to provide an inherent resistive termina- tion via external networks. the codec will then provide gain shaping, as a function of frequency to meet the return loss requirements. further stability issues may add external components or excessive ground plane requirements to the design. to meet the unique requirements of both types of codecs, the l9219 offers two receive gain choices. these receive gains are mask-programmable at the factory and are offered as two different code variations. for interface with a first-generation codec, the L9219A is offered with a receive gain of 7.86. for interface with a third-generation codec, the l9219g is offered with a receive gain of 2. in either case, the transconductance in the transmit direction, or the transmit gain, is 403 w . example 1: real termination (first-generation codec) ac equivalent circuits for real termination using a t7504 codec is shown in figure 23. figure 16. ac equivalent circuit r p z t + C r p v t/r i t/r v s z t/r + C ring a v = C1 a v = 1 vitr C + + C current sense tip + C r t1 r rcv r hb1 r t2 rcvn rcvp r x vgsx vf x in vfr 1/4 t7504 codec r g 2.4 v C0.403 v/ma a v = l9219 slic vf x ip 3.93 12-3581 (f).c
24 24 agere systems inc. data sheet november 2001 with reverse battery and dual current limit L9219A/g low-cost line interface applications (continued) ac design (continued) example 1: real termination (first-generation codec) (continued) the following design equations refer to the circuit in figure 16. use these to synthesize real termination imped- ance. termination impedance: z t = receive gain: g rcv = g rcv = transmit gain: g tx = g tx = x hybrid balance: h bal = 20log to optimize the hybrid balance, the sum of the currents at the vfx input of the codec op amp should be set to 0. the following expressions assume the test network is the same as the termination impedance: r hb = h bal = 20log v tr i tr C -------------- z t 2r p 3168 1 r t3 r gp -------- - r t3 r rcv ----------- - ++ ----------------------------------- + = v tr v fr ------------- - 7.86 1 r rcv r t3 --------------- r rcv r gp --------------- ++ ? ?? 1 z t z t/r ------------ - + ? ?? ------------------------------------------------------------------------------------- v gsx v tr -------------- - r x r t6 ---------- 403 z t ---------- - v gsx v tr -------------- - r x g tx g rcv ------------------------ - r x r hb ----------- - g tx C g rcv ? ??
agere systems inc. 25 data sheet november 2001 with reverse battery and dual current limit L9219A/g low-cost line interface applications (continued) ac design (continued) example 2: complex termination (first-generation codec) below are design equations for complex termination (see figure 17 and figure 18). z t = r t1 + r t2 || c t r tgp || r tgs r tgp || r tgs g tx = g rcv = h bal = 20log where: z t/r = r 1 + r 2 || c z tg = r tgp || (r tgs + c g ) r tgp = 8.06 k w r tgs = r tgp c g = x c and c n r n2 = c g r tgp r n1 = r n2 the equations above do not include the blocking capacitors. r t1 2r p 7.86 201.2 ----------- - 1 1 r t3 r gp -------- - r t3 r rcv ----------- - ++ ----------------------------------- 1 1 r n1 r n2 -------- + ----------------- - C ? ? ? ?? + = r t2 7.86 201.2 ----------- - r tgp r tgs 1 r t3 r gp -------- - r t3 r rcv ----------- - ++ ----------------------------------- 1 1 r n1 r n2 -------- + ----------------- - + ? ? ? ?? = 1 c t ------- 7.86 201.2 ---------------- 1 c n1 ---------- - r n2 r n1 r n2 + () 2 ------------------------------------ - r tgp r tgs || 1 c tg ---------- - r tgp r tgp r tgs + ------------------------------------ - ? ?? 2 1 1 r t3 r gp ----------- - r t3 r rcv --------------- ++ ---------------------------------------------- 1 1 r n1 r n2 ---------- - + --------------------- C ? ? ? ? ?? + ? ? ? ? ? ? = r x r t6 ---------- 1 201.2 ---------------- z tg z t ---------- - 7.86 1 r rcv r t3 --------------- r rcv r gp --------------- ++ ----------------------------------------------- - 1 1 z t z tr ------------- + ----------------------- - r x r hb ----------- - g tx C g rcv ? ?? r 1 r 2 ------- r 2 2 r tgp r 1 r 2 + () ------------------------------------------ 2r p 3038 ------------ - 3038 2r p ------------ - r tgs r tgp ------------- - ? ?? 1 C
26 agere systems inc. data sheet november 2001 with reverse battery and dual current limit L9219A/g low-cost line interface applications (continued) ac design (continued) example 2: complex termination (first-generation codec) (continued) figure 17. interface circuit using first-generation codec ( 5 v battery) figure 18. interface circuit using first-generation codec (5 v only codec) r tgs r tgp = 8.06 k w r t6 r x r t3 codec op amp C + c n r n1 r n2 r gp r rcv r cvn r cvp Ci t/r 201.2 c gs c b r tgs r t6 r t3 codec output drive amp codec op amp C + c n r n1 r rcv rcvn rcvp Ci t/r c gs ax aac 5-6401 (f).j r tgs c b r tgp = 8.06 k w r t6 r x r t3 codec output drive amp codec op amp C + c n r n1 r n2 r gp r rcv rcvn rcvp Ci t/r 201.2 c g ax C2.4 v aac c b1 c b2 5-6400 (f).n
agere systems inc. 27 data sheet november 2001 with reverse battery and dual current limit L9219A/g low-cost line interface applications (continued) power derating operating temperature range, maximum current limit, maximum battery voltage, minimum dc loop, and pro- tection resistor values will influence the overall thermal performance. this section shows the relevant design equations and considerations in evaluating the slic thermal performance. consider the l9219 slic in a 28-pin plcc package. the still-air thermal resistance on a 2 layer board is 43 c/w. the slic will enter the thermal shutdown state at mini- mally 150 c. the thermal shutdown design should ensure that the slic temperature does not reach 150 c under normal operating conditions. assume a maximum ambient operating temperature of 85 c, a maximum current limit of 25 ma (including tol- erance), and a maximum battery of C52 v. further- more, assume a (worst case) minimum dc loop of 200 w , and that 50 w protection resistors are used at both tip and ring. 1. t tsd C t ambient(max) = allowed thermal rise. 150 c C 85 c = 65 c 2. allowed thermal rise = package thermal impedance ? slic power dissipation. 65 c = 43 c/w ? slic power dissipation slic power dissipation (p diss ) = 1.51 w thus, if the total power dissipated in the slic is less than 1.51 w, it will not enter the thermal shutdown state. total slic power is calculated as: to t a l p diss = maximum battery ? maximum current limit (including effects of accuracy) + slic quiescent power. for the l9219, slic quiescent power (p q ) is maximum at 0.158 w. thus, to t a l p diss = (C52 v ? [25 ma ? 1.05]) + 0.158 w to t a l p diss = 1.365 w + 0.158 w to t a l p diss = 1.523 w the power dissipated in the slic is the total power dis- sipation minus the power that is dissipated in the loop. slic p diss = total power C loop power loop power = (i lim ) 2 ? (r dcloop min + 2r p ) loop power = (25 ma ? 1.05) 2 ? (200 w + 100 w ) loop power = 0.207 w slic power = 1.523 w C 0.207 w = 1.28 slic power = 1.28 w < 1.51 w thus, in this example, the thermal design ensures that the slic will not enter the thermal shutdown state. pin-for-pin compatibility with l9217/l9218 the l9219 is an exact pin-for-pin replacement for the l9217/18. the one minor exception is l9219 has three logic control inputs: b0, b1, and b2. the l9218 has only two logic control inputs, b0 and b1. pin 13 in l9218 is nc, so a connection between the controller and pin 13 will not affect l9218 operation. this allows an exact footprint match with l9219. pcb layout information make the leads to bgnd and v bat as wide as possible for thermal and electrical reasons. also, maximize the amount of pcb copper in the area of (and specifically on) the leads connected to this device for the lowest operating temperature. when powering the device, ensure that no external potential creates a voltage on any pin of the device that exceeds the device ratings. in this application, some of the conditions that cause such potentials during pow- erup are the following: 1. an inductor connected to pt and pr (this can force an overvoltage on v bat through the protection devices if the v bat connection chatters). 2. inductance in the v bat lead (this could resonate with the v bat filter capacitor to cause a destructive over- voltage). this device is normally used on a circuit card that is subjected to hot plug-in, meaning the card is plugged into a biased backplane connector. in order to prevent damage to the ic, all ground connections must be applied before, and removed after, all other connec- tions.
28 28 agere systems inc. data sheet november 2001 with reverse battery and dual current limit L9219A/g low-cost line interface outline diagram 28-pin plcc dimensions are in millimeters. 1.27 typ 0.330/0.533 0.10 seating plane 0.51 min typ 4.572 max 12 18 11 5 4126 25 19 12.446 0.127 pin #1 identifier zone 11.506 0.076 11.506 0.076 12.446 0.127 5-2506 (f)r.8
agere systems inc. 29 data sheet november 2001 with reverse battery and dual current limit L9219A/g low-cost line interface ordering information device package comcode lucL9219Aar-d 28-pin plcc (dry bag) gain of 12 108558867 lucL9219Aar-dt 28-pin plcc (tape and reel, dry bag) gain of 12 108558875 lucl9219gar-d 28-pin plcc (dry bag) gain of 2 108558800 lucl9219gar-dt 28-pin plcc (tape and reel, dry bag) gain of 2 108558818
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